U.S. Pat. No. 4,672,581 describes a memory circuit comprising a memory array having a plurality or rows and columns, a plurality of column decoders for enabling access to columns in said array, each column decoder being associated with a respective group of said columns and being arranged to selectively access one of the columns in the respective group, and further comprising a spare group of memory columns and a further column decoder associated with said spare group of columns and arranged to selectively access one of the columns in said spare group, and logic means programmable to inhibit access to a selected group of said columns. Each group has associated with it a data line for reading and writing data from and into selected memory cells.
The data line for each group can be connected either to that group or to the adjacent preceding group. The data line of the first group can be connected either to the first group or to the spare group. In this circuit, any selected group of columns which is found to be defective can be replaced by the adjacent preceding group of columns. However, despite the proximity of the groups there will be some increase in access time due to the extra loading associated with the connecting circuitry between adjacent datalines. The data line of the replacement group is connected to the next preceding group and so on until the data line of the first group is connected to the spare group of columns.
Each row of the memory array is arranged to store more than one data word, only one data bit of each data word being stored in any one group of columns. Further, the number of columns in each group is equal to the number of data words to be stored in each row, and the number of groups of columns is equal to the number of data bits making up each data word. Correspondingly positioned bits of each data word are then stored in each group of columns.
Transistors are arranged to connect each data line to its associated group of columns or to the preceding group, according to the location of faulty columns apparent during testing. The connections of the data lines can be selected by blowing fuses.
With the repairable memory circuit described above, the column decoder associated with the spare group of columns is connected to the data line of the next adjacent group so that a whole group of columns containing the faulty column is replaced by a whole group of spare columns. This means that, for example for the case where each group contains sixteen columns then sixteen columns are required for each level of redundancy. By each level of redundancy is meant the number of groups in which faulty columns are replaced by spare columns.
Also, the connection of the data line associated with one group to the next preceding group incurs a penalty in terms of an increased signal path length. In U.S. Pat. No. 4,672,581 this penalty is incurred where the data line signal is developing during a read cycle, i.e. between the read/write circuitry and the column decoder, hence entailing an undesirable additional load on the developing data line signal.
It is desirable to reduce this load, particularly for fast access static random access memories (SRAMs), so that the time taken to achieve a bitline differential sufficient for sensing is not impaired. It is further desirable to increase the efficiency of repair of the memory circuit.